System level synthesis for low power media processors

Die size and power consumption are the two most important design goals for embedded systems, particularly consumer mobile devices. Although mobile devices such as personal digital assistants, MP3 players and smart phones have fixed performance requirements, they nevertheless possess unlimited appetites for reduced cost and increased battery life. Traditionally, embedded systems have been optimized for specific tasks. They were usually custom-made chips tuned for their particular applications and low power requirements. As mobile devices are getting more advanced, a handheld today can be used to capture not just still images but also live videos in addition to browsing the web with wireless protocol and preserving the capability of a digital assistant. Since running the application any faster than necessary is a waste of energy and reduces battery lifetime, designing a modern low power media processor for today's embedded systems suitable for various applications is becoming more challenging than ever before. The arrivals of production quality instruction level parallelism (ILP) compilers and commercial DSPs with VLIW and SIMD architectures stimulated the idea of custom-fit processors. The premise of such approach is that applications differ from one another in exploitable measures, such as the available HP, the demand on various hardware components (e.g. cache memory units, register files), and the number of function units.; To target the issues of automatic synthesis, we develop a framework of system-level synthesis based not only on performance and area but also on power using an aggressive ILP compiler toolset and a benchmark that represents the overall multimedia industry.; Because today's embedded systems run multiple computation-intensive media applications at the same time and most often with Quality of Service in mind, we introduce a low power hypermedia processor system and different synthesis algorithms that examine a category of processors that are programmable but aggressively optimized to reduce power consumption for specific set of applications while addressing the need for maximizing net benefit of a system under resource constraints with a QoS-based system partitioning scheme.