| In this thesis, we will address post-manufacturing power-aware computing at the system-level for real-time and multimedia systems. We divide the system-level domain into four layers: the microarchitectural, compiler, operating system and network. We will isolate and examine two main tracks. First, we will show in Chapter 2 that the current system-level power savings methods are piecemeal approaches, not even comprehensively addressing single issues within the layers. We will be capitalizing on this research gap and our contribution will be to consider inter- as well as intra-layer system-level power-savings. By this, we mean that we will examine energy management across system layer boundaries: the network/OS or the compiler/hardware layers for example. Second, although there is some previous research in system-level power issues in real-time systems, much remains to be done; especially for developing new power-aware heuristics specifically for real-time systems.; Historically, the main performance metrics in complex real-time systems has been timeliness, determinism and fault tolerance. Power-aware issues require new performance measures: power and energy efficiency. These new metrics imply new approaches and novel heuristics.; In line with the above vision, we will be looking into the energy implications of task assignment and scheduling algorithms, communication protocols, network topology, data redundancy, fault tolerance, predictability, node architecture, compiler and operating systems, all of which span multiple layers and are important concerns in real-time and embedded systems.; This thesis is organized as follows: In Chapter 1, we introduce the problem and develop our approach. In Chapter 2, we survey previous work which will expose the void that we aim to fill. In Chapter 3, we report on our work at the Network/Operating System (OS) layers. Chapter 4 discusses power-aware fault tolerance, an OS level contribution. In Chapter 5, we lay the ground for the compiler-related aspects of our analysis. Chapters 6 and 7 discuss two compiler-microarchitectural level power-aware data-cache designs. Chapter 8 introduces a microarchitectural-level fetch-throttling scheme. We conclude with future work in Chapter 9. |
