6GHz Active-Inductor Matched Duplexer-Iess LNA/PA Design Incorporated with a Bondwire-Antenna

A design technique and detailed design equations for a high frequency (above 6GHz), high-Q, active inductor (AI) is discussed using non-minimal-length CMOS technologies, such as 130nm CMOS, which can be attractive because of the bias controls available in the discussed novel topology can regulate its performance over process variations. The design is achieved via a parasitic cancellation technique. An inductance of 1.9nH is acheived at 6.75GHz with a Q of 38. The active inductor is then used to obtain a high-gain, narrowband, tuning and a output-matching element at or above 6.5GHz.;The last part of this thesis discusses the design of a bondwire antenna with detailed equations showing the derivation of the radiated power, radiation pattern, and the transmitter to receiver link-budget for a bondwire-antenna for short-range radio communications in the 6.5GHz frequency range. The bondwire antenna is then used to design a high-gain, narrowband duplexer-less LNA/PA block for a transceiver with the LNA input and PA output automatically matched to the bondwire-antenna. Besides the inductive bondwire antenna, the LNA and PA are designed to be inductor-less, thus saving silicon chip area. The transceiver range is calculated to be about 4.86m, ideal for applications such as remote controls, biomedical monitoring equipment, or RFID tags. Both front end blocks are designed with low-power, low cost and high yield considerations. The inductorless LNA parameters at 6.5GHz are a S21 of 14.7dB, a NF of 4.9dB, S11 and a S22 less than -10dB. Also, a S21 of 14.4dB is achieved for the PA. A power consumption of 9.8mW for the transmit (TX) and 14.6mW for the receive (RX) is achieved using a 1.2V supply.;Also discussed is a design procedure for designing low-power narrowband high-gain CMOS LNAs for wireless applications at frequencies greater than 6GHz, with considerations for process variations. This procedure, used to design the LNA and test the AI, is not based on detailed derivations of equations; rather it is based on a simulation procedure and methodology that converges quickly to a practical optimized solution for LNA designs. As a result, it requires minimal time and resources from the designer. It takes a holistic design approach where all factors, including manufacturing costs, technology choice and applications are considered. The procedure conveys how to design the appropriate topology from the "ground up", and then gives the designer the option to match the ports or not; depending on if it is necessary or appropriate. The inductorless LNA specifications at 6.5GHz are: a S21 of 14.7dB, a NFmin of 3.3dB, a NF of 6.2dB and a S22 less than -15dB with only 6.4mW (plus 2.5mW for narrow-band output match) power consumption for a 1.2V supply. It should be noted that the use of the AI severely reduces the linearity of the circuit to a 1-dB compression point of -26dBm. This limits the range of operation of the LNA when used in a transceiver, but saves chip area and production costs.