Recrystallized silicon pillar MOSFETs for high density DRAM cells

Dynamic random access memory (DRAM) is an important technology driver for the semiconductor industry. In order to meet industry demands to store larger and larger amounts of data in a small chip area, devices have had to be continuously scaled down. For DRAM devices beyond 4 Gigabits however, the conventional method of fabrication will no longer be viable because of the high subthreshold leakage current in the access transistors. The objective of this thesis work is to investigate potential solutions to this problem by developing a new recrystallized silicon pillar transistor.; A recrystallized-Si pillar (vertical) transistor is formed on top of a trench capacitor with the top of the pillar transistor directly connected to the bit line. This vertical structure forms a 4F2 cell reducing the cell area of a conventional 8F2 cell by half. The proposed fabrication processes are far simpler and require fewer mask steps than conventional DRAM cell technology.; The material properties of recrystallized-Si pillars were investigated by cross sectional TEM analysis. As the pillar size decreased, the probability of obtaining a single grain structure increased. The mechanisms behind single grain formation were heterogeneous nucleation at the bottom of the pillar and an orientation dependent growth rate.; An analytical model for surrounding gate MOSFETs including bulk traps was investigated. Based on the depletion approximation and the assumption that bulk traps are uniformly distributed inside the bandgap, Poisson's equation in cylindrical coordinates was solved. The model predicts that the threshold voltage and subthreshold swing increase as the trap density increases. The analytical solution yields good agreement with MEDICI simulations confirming the model.; Electrical measurements showed that the recrystallized-Si pillar transistor exhibits good subthreshold slope and Id-Vd characteristics. Improvements in the device performance were achieved by sacrificial oxidation and hydrogenation. By controlling the channel doping and gate oxide thickness, partially depleted (PD) and fully depleted (FD) transistors were fabricated.; Materials analysis, modeling, and measured device characteristics indicated that device performance improves with scaling. Therefore, recrystallized-Si pillar MOSFETs are a promising candidate for future DRAM access transistors.