| For over three decades, the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has successfully undergone scaling to improve performance, and is presently at the sub-100 nm technology node. This has been possible due to several advances in the field, such as the introduction of copper interconnects, low-K dielectrics, silicided contacts, source-drain extensions, etc. Future scaling will require new materials such as strained silicon or silicon-germanium for channel mobility and drive current enhancement, high-K gate dielectrics to reduce the gate leakage current, and novel devices such as vertical MOSFETs or Fin-FETs to suppress short-channel effects.; In this work, we have fabricated sub-100 nm silicon-based vertical MOSFETs, such as 70 nm strained and unstrained silicon-germanium vertical MOSFETs, 90 nm vertical MOSFETs with hafnium-oxide gate dielectric deposited by chemical vapor deposition (CVD), and a novel 50 rim Dielectric Pocket Vertical MOSFET (DPV-MOSFET) that shows excellent suppression of short channel effects. All samples were grown with the help of Ultra-high Vacuum Chemical Vapor Deposition (UHVCVD).; We have demonstrated improved hole mobility and drive current in the SiGe PMOSFETs with a uniform Ge profile. However, the SiGe devices also had a higher leakage current and lower breakdown voltage due to the smaller bandgap of SiGe as compared to Si. The unstrained SiGe vertical MOSFETs were grown on a relaxed SiGe virtual substrate, and did not show a mobility enhancement, indicating that the improvement in mobility in strained SiGe is due to strain in the crystal lattice and not just Ge content.; We observed conformal dielectric deposition and reduced gate leakage currents in the vertical MOSFETs with hafnium-oxide deposited by Rapid Thermal Chemical Vapor Deposition. The SiGe devices with CVD-HfO2 gate dielectric showed improved drive currents.; We also fabricated a novel device called the DPV-MOSFET. Introduction of a dielectric pocket at the source-channel junction results in a device with a shallower equivalent source junction depth and hence reduced short channel effects such as VT-rolloff and drain induced barrier lowering (DIBL). Simulation results indicate that the device also a higher ION/I OFF ratio. |
