Silicon carbide MOSFETs

Key process technologies for the fabrication of SiC MOSFETs, especially UMOSFETs, are developed. The characterization results of SiC MOSFETs including a modified UMOSFET are presented. A complete device fabrication procedure is attached in the appendix. Key processes include ohmic contacts to SiC, SiC MOS, and SiC etching.; For ohmic contacts to SiC, we fabricated silicide contacts to SiC using two different approaches. For direct metal silicide contacts, a number of metals including nickel and palladium were investigated. For silicon interlayer silicide contacts, palladium silicide contacts were investigated. The extracted specific contact resistance was 1.0 × 10−4 $W$-cm2 for direct Ni contacts fabricated on n-type 6H-SiC after annealing at 950°*C in forming gas. For SiC MOS, we investigated two different types of MOS diode structures. For single dielectric MOS diode structures, we investigated thermal dry oxide and PECVD oxide. For stacked dielectric MOS diode structures, we investigated both silicon nitride and silicon dioxide deposited by PECVD onto thermally grown thin silicon dioxide on n-type 6H-SiC.; For the etching of SiC, we investigated magnetically enhanced reactive ion etching of SiC in mixtures of sulfur hexafluoride (SF₆) with argon (Ar). Etching using SF₆/Ar gave an etch rate as high as 1900 Å/min. Atomic force microscopy showed that surface roughness of etched SiC decreased from 6.1 to 4.4 Å rms, and scanning electron microscopy showed good etch anisotropy. This etching with smooth surfaces, high etch rates, and good etch anisotropy is useful for SiC power UMOSFETs and other device structures.; For SiC MOSFETs, we fabricated and characterized SiC lateral MOSFETs (LMOSFETs) and SiC vertical UMOSFETs. The extracted field effect mobility was 7.5 cm2/V-sec for the LMOSFET and 2.6 × 10 −3 cm2/V-sec for the UMOFET. Non-linearity at low drain bias was observed in both devices. Through SEM examination, we found a trench along the edge of etched features that interrupted the current path between an inversion channel and a source/drain region. Although the mobility of 7.5 cm2/V-sec for the LMOSFET is lower than the best reported mobility for SiC MOSFETs, this is the highest field effect mobility reported for MOSFETs with an inversion channel on an etched surface.