A VLSI implementation of an adaptation algorithm for a pre-emphasis in a backplane transceiver

This thesis uses an adaptive pre-emphasis technique to compensate for channel inter-symbol interference (ISI) on a typical copper backplane. Functional models and Matlab code have been developed to verify the effectiveness and efficiency of the adaptation and equalization process using a sign-sign block least-mean-square (LMS) adaptive algorithm. The pre-emphasis structure covered in the simulation is a linear transversal type. The pre-emphasis and the adaptive algorithm are modeled using various simulation modules covering three different channel models. Both 2-level pulse amplitude modulation (PAM) and 4-level PAM are used in simulation. Using 4-PAM reduces the symbol rate by half compared to the conventional 2-PAM system. This symbol rate reduction relaxes the requirement for the channel bandwidth by a factor of two and allows the on-chip clock frequency to be reduced to half of the original.; Two different hardware structures of a sign-sign block LMS algorithm for an adaptive pre-emphasis in a copper backplane transceiver have been implemented in Verilog targeting the TSMC 0.18um CMOS technology. One structure is the round-robin adaptation engine that updates tap coefficients every four blocks of data. This structure was proposed by Accelerant Networks in 2002. The other is the proposed structure, called the parallel adaptation engine. It updates tap coefficients every block of data. Simulation (or Synthesis) results show that digital standard cells can be directly applied to both structures to achieve 625 MHz timing constraints. A custom circuit is not needed to implement the digital adaptation algorithm for an analog adaptive pre-emphasis up to 625 MHz.; This research work has shown that the transmit adaptive pre-emphasis technique used here is a simple and cost-effective way to achieve a high data rate (up to 5 Gb/s) on typical copper backplanes as described above using 4-PAM modulation.