Digital circuit design through simulated evolution

Evolutionary computation presents a new paradigm shift, in hardware design and synthesis. The new paradigm is expected to radically change the design procedure such, that new possibilities for discovering novel designs and/or more efficient circuits can emerge. In this thesis, Simulated Evolution (SimE) algorithm is used for combinational logic design. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation steps of SimE. Area, power and delay are considered in the optimization of circuits. The performance of the proposed algorithm is evaluated using selected ISCAS'85 benchmark and a set of randomly generated circuits. The results obtained are compared to other techniques in terms of power, area and delay. It is shown that the results of the proposed techniques are better in terms of quality and time.