| Asynchronous Transfer Mode (ATM) communication is a maturing technology. As data rates increase towards 2.4Gbps and beyond, a scaleable architecture is desirable. A system-on-a-chip (SoC) approach is used to solve this problem. Utilizing custom intellectual property developed in the VLSI and Computer Design Laboratory at Simon Fraser University, a 622Mbps ATM Adaptation Layer five (AAL5) segmentation architecture is proposed. The ATM Transmitter (ATMT) takes a number of channels of data and breaks them up into packets and schedules them for transmission over an ATM network. The segmentation/transmission unit is designed to complement the 622Mbps reassembly unit (ATMR) already designed by our laboratory. Together, the segmentation and reassembly unit would form a two chip or single chip solution for a User-Network Interface (UNI) inside an ATM network leaf cell (a personal computer for example).; The algorithm for the scheduler is written in assembler and comprises a large part of the firmware for the processors. (Abstract shortened by UMI.)... |
