Stacked FSMD: A new microarchitecture model for high-level synthesis

High-Level synthesis is a process that automates the transformation of an algorithmic description of a digital design into its physical implementation. With digital systems' ever increasing complexity in terms of transistor count and clock speed, it becomes necessary for a high-level synthesis tool to work; Traditional high-level synthesis tools are unable to efficiently synthesize or Java. This is because the Finite State Machine with Datapath model (FSMD), the underlying microarchitecture into which the synthesis tool transforms the design, is too simplistic. FSMD is unable to effectively capture; This thesis makes two primary contributions: First, it proposes an extension of the FSMD model into a Stacked FSMD (SFSMD) model that supports procedure it describes a behavioral level partitioning technique which leverages the SFSMD model to reduce power consumption.