Application-specific external memory interfacing for FPGA-based reconfigurable architecture

The flexibility of Field-Programmable-Gate-Arrays (FPGAs) has made them the medium of choice for fast prototyping and a popular vehicle for the development of custom hardware designs for reconfigurable computing. Despite their popularity, FPGAs are hard to program and existing programming tools lack support for the external memory operations.; In this thesis we describe a decoupled memory interface (DMI) design approach to support external memory operations targeting reconfigurable devices such as FPGAs. The proposed approach directly supports an FPGA macro data-flow execution mode; where the computation is defined as a behavioral Very-High-level-Description-Language (VHDL) process interacting with the external memory via the notion of data streams. These abstract concepts of tasks and data streams are pervasive in image and signal processing computation for which FPGAs has been recognized to be an excellent match.; The proposed solution also allows for the effective integration of behavioral VHDL with Register-Transfer-Level specifications, therefore which takes advantage of a wealth of synthesis techniques for behavioral specification while promoting modular development of multiple interacting designs---a notoriously difficult problem for large designs enabled by the increasing capacity of FPGA devices. We have successfully integrated the design approach presented in this thesis with a compilation and synthesis tool that combines behavioral synthesis with structural synthesis for VHDL designs.; The increased FPGA device capacity has enabled the development of system-on-a-chip with multiple and heterogeneous processing cores connected via a programmable interaction network. Future systems with these characteristics will, undoubtedly, need to communicate with external, or even multiple, internal memory modules. Because of the heterogeneity of these future platforms, the development of flexible interfaces, such as the one proposed here, will allow the rapid development of complete and correct designs. The ability to generate a large number of complete and correct designs will ultimately lead, we believe, to better and more reliable design exploration strategies with which compilation tools can deliver effective designs in useful time.