| The rigorous scaling down of CMOS critical dimensions according to Moore's law has resulted in increased device integration densities, higher transistor switching speeds and therefore an exponentially growth of cost-effective computing power (bits) - 1000X performance improvement over the past 20 years. However, current microprocessors are becoming rapidly limited in chip-scale interconnect capacity. On-chip global interconnections and off-chip communications do not scale commensurately with the device sizes, resulting in a host of challenges to meet the growing bandwidth requirements without expending excess power.;Microprocessor power consumption, with a large fraction contributed by chip-level interconnects, is becoming a new fundamental barrier for high performance computing (HPC) systems to continue their performance scaling trend. With state-of-the-art HPC systems operating near the 1GFLOPS/W (109 floating-point operations per second/watt) level, it is projected that chip-level electrical interconnects will limit the system performance at ∼6GFLOPS/W, due to the energy efficiency barrier posed by metal wires. In order to realize systems with "PetaFLOPS-in-a-rack", microprocessors with performance over ∼10TFLOPS/chip are required, corresponding to 10's of GFLOPS/W. The energy efficiency target for chip-level interconnects strongly suggests that alternative approaches, most likely optical interconnects, should provide a power budget in the sub-pJ/bit domain and keep pace with the bandwidth requirement as the chip performance continues to improve.;In this thesis, solutions based on novel integrated photonic systems are presented, utilizing surface-normal multiple quantum well (MQW) modulators heterogeneously integrated onto a silicon chip and linked by multimode polymer waveguides, leading to high bandwidth density, low power consumption optical fabrics and seamless interfacing between on- and off- chip domains. The work presented here are the first to demonstrate a waveguide-coupled surface-normal MQW-based approach that is fully integrated within a photonic layer and to a large extent mitigates packaging issues for future photonics systems integrated with Si chips. Key notions are efficient and minimum-footprint optical fabrics and low-power-consuming optical transceivers. Gray-scale lithography is used to fabricate to 3D coupling structures directly in the waveguide polymer layer. From analyses and experimental results, the proposed optical fabrics can potentially offer the necessary bandwidth density and low power consumption for future chip-scale interconnections. The proposed high-capacity optical interconnect approach, which would have back-end CMOS compatibility, is a potential solution to overcome the limits of electrical interconnects at the chip level. |
