A compiler infrastructure for compiling assembly and binary programs onto FPGAs

The unprecedented growth of the Internet, broadband and wireless communications has created an insatiable market for the electronics industry. Increasing demand has provided opportunities for the growth of embedded software, operating systems and development tools. Hardware technology is also evolving faster than ever before. Software developers are under increased pressure to develop a large number of more complex embedded software projects in less time.; Field-Programmable Gate Array (FPGA) architectures, with DSP support, provide a new hardware alternative for DSP designers, allowing them to attain greater levels of performance than on common DSP processors. Until now, the design process for this platform has been tedious. This research project aims to provide a framework for a new design methodology that automatically generates hardware designs for these platforms. It investigates the process and considerations for automatically translating software binaries into Register Transfer Level (RTL) VHDL or Verilog code. The techniques are based on compiler theory, behaviour synthesis, and graph theory. They represent novel algorithms and heuristics and have been implemented in a compiler, FREEDOM. The compiler has been used to illustrate the techniques and present performance results.; The goal of this research has not been to compete with the best manual implementation of DSP algorithms on an FPGA, but to show that it is possible to seamlessly migrate legacy assembly code for a state-of-the-art DSP processor to hardware and still get 2--5X improvement in performance. Optimizations have been designed and implemented towards improving performance of the design. Non-profiling based procedure extraction techniques have been designed to extract procedure bodies from assembly code and generate a call graph. This call graph is utilized to partition the design. Most previous work on control and data flow analysis has assumed the presence of a single procedure. This is satisfactory for compilation proceeding from high-level languages. This assumption does not hold for the current decompilation task. Interval and control flow analysis techniques have been modified to handle the new conditions.; A new semantic language has been designed. It is used in combination with a syntax description language to fully describe the syntax and semantics of processor Instruction Set Architectures. The descriptions generate a retargetable front-end for the compiler. It is powerful enough to handle CISC and VLIW architectures with parallel and predicated constructs.; The compilation tool has allowed us to make some interesting observations and is greatly aiding in the exploration of avenues of further research.