| This thesis describes an implementation of a simple but complete digital communication chain on an FPGA development system. The implementation has the following elements: modulator, demodulator, channel, channel estimator and bit error rate (BER) counter.; The additive white Gaussian noise (AWGN) generator is based on the combination of the Box-Muller method and the Central Limit Theorem. The Rayleigh channel and channel estimator are based on Young and Beaulieu's method and the sinc interpolator method, respectively. Their performances are verified by comparisons between computer simulations and true hardware operation.; The implementation results obtained show that the performances of the digital communication chain with the BPSK, QPSK, 16-QAM and 64-QAM modulation schemes are close to the computer simulation results for both the AWGN and the Rayleigh channel models. The channel estimation technique we use in this thesis is the pilot symbol assisted modulation (PSAM) which is one of the many channel sounding techniques to be effective for the Rayleigh fading channel. The implemented systems with the channel estimator are superior in performance to any systems without a channel estimator. The implementation has a simple structure, use less resources, and offers flexibility for future uses. |
