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Amorphous silicon vertical thin film transistor

Posted on:2006-05-30Degree:Ph.DType:Thesis
University:University of Waterloo (Canada)Candidate:Chan, IsaacFull Text:PDF
GTID:2458390008955669Subject:Engineering
Abstract/Summary:
This thesis focuses on the design of vertical thin film transistors (VTFTs) in hydrogenated amorphous silicon (a-Si:H) technology. This novel transistor structure offers a new method for fabricating submicron channel length TFTs in a vertical orientation. Another attractive feature of the vertical transistor structure is that it inherently occupies a much smaller device area than the lateral TFTs by standard lithography. Therefore, short-channel and small-area TFTs can be fabricated by a low-cost process using conventional photo-etching equipment, and without the need for nanolithography.; The key for taking the vertical device concept to practice lies in realizing a successful anisotropy dry etching technique for the vertical drain-source multilayer structure. Thin film deposition, photolithography, and dry etching are therefore systematically optimized for the VTFT fabrication. A thick film photoresist process is developed with a thickness up to 6.6 mum, a lithographic resolution down to 1 mum, and a highly vertical resist profile of more than 80° for accurate device pattern transfer on a non-planar surface. A dry etch process with 100% anisotropy is developed for the vertical device structure by utilizing a CF4/H2 plasma.; The a-Si:H VTFT reported in this work advances the state-of-the-art designs, by demonstrating the first 0.1-mum channel length VTFT with an ON/OFF current ratio greater than 108. This is, by far, the shortest channel a-Si:H TFT ever reported. With the proper design of the gate dielectric thickness, short-channel effects can be considerably suppressed for viable device operation. In addition, the parasitic overlap capacitances of the VTFT are very small, lower than 50 fF, due to the compact size of the VTFT. Such an achievement is conducive to fast switching dynamic performance.; Lastly, the VTFT structure presented in this work allows the novel design of a VTFT active-matrix backplane with a TFT-size independent fill factor. We have demonstrated a 26 x 26, 65-mum pitch VTFT array prototype, which is easily scalable to large areas. The a-Si:H VTFT technology developments reported here offer a great promise for a new generation of high-resolution flat-panel electronics.
Keywords/Search Tags:VTFT, Vertical, Thin film, A-si
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