Circuit design for low voltage wireless receiver with improved image rejection

In a typical wireless receiver incoming RF (Radio Frequency) signal is down-converted to a lower IF (Intermediate Frequency) signal to relax the signal processing requirements of subsequent stages. A down-conversion mixer is used for translating desired signal to a signal with lower frequency. Mixer has two input-one comes from local oscillator, with a signal frequency of o LO and other from incoming RF signal with frequency oRF. After mixing with analog mixer the desired RF signal is down-converted to a lower IF signal such that oIF = oRF - o LO. But due to the properties of sinusoidal multiplication with this analog mixer, signal band that is located symmetrically below o LO, such that oIM = oLO - o IF, also downconverted to IF frequency. Here colts is the location of another signal. Hence, besides desired RF signal, another undesired signal located at oIM also translated to oIF. This undesired signal is known as image interferer, must be rejected to prevent aliasing with desired signal. External high Q filters are required to remove the image. This off-chip filter continues to be a bottleneck for realizing complete receiver integration. Image-reject receiver such as Weaver and Hartley architecture does not use off-chip image reject filter. But they are sensitive to mismatches of the two quadrature signal path that limit the image rejection ratio (IRR). In this thesis issues with image problem has been observed. The effect of mismatch has been studied for Weaver and Hartley image reject receiver by mismatch modeling. A simple but effective phase calibration technique without using any external calibrating tone has been developed to improve the IRR. It has been implemented for Weaver and Hartley image reject receiver. In both cases image rejection ratio (IRR) of more than 59dB can be achieved for phase mismatch of 2 degree and small gain mismatch. Hence integrated receiver with improved IRR can be implemented without off-chip image reject filter and can be realized for standard like GSM (Global Systems for Mobile Communication), WCDMA (wideband Code Division Multiple Access) where higher IRR are required. Also to achieve programmability and multi-standard capability, low voltage low power circuits are essential. Designing such circuits always has been a major challenge. After downconversion of RF signal, entire signal processing is done in baseband. Low voltage and low power baseband circuits are necessary to provide low cost integrated receiver with added portability. In this dissertation low voltage circuit design techniques have been discussed for some essential baseband blocks of receiver such as variable gain amplifier (VGA), buffer and filter. VGA is used for gain variation between different block of the baseband and thus reduce noise requirements of subsequent blocks. CMOS realization of low noise and high bandwidth VGAs are presented. The simulation for the VGA is performed in TSMC .18mu technology. VGA's can be designed for input referred noise as low as 6nv/√Hz at 100 KHz and 3-dB bandwidth of more than 500 MHz. Highly linear baseband filters are required for channel selection of receiver. In this dissertation a novel low voltage buffer with low power consumption and low input referred noise has been used in Sallen-Key structure to realize channel select filter [3].