Binary phase-shift keying demodulator with anti-parallel synchronization method

An anti-parallel carrier synchronization method for BPSK is proposed and demonstrated in this thesis, which results in a new compact BPSK demodulator for coherent digital communications. The method contains an anti-parallel dual loop, which locks the carrier by its upper loop and low loop alternately according to the received data bits. The method is similar as the Costas loop but with simpler and more easily integrated elements, so the entire demodulator system will be very compact if it is implemented on integrated circuit technology compared with the Costas loop. Moreover, with the elimination of the 90° phase shifter used in the Costas loop, this demodulator concept has flexible carrier frequency tuning and thus is very suitable for multi-band communication systems.; In this thesis, the fundamental operating principle of the proposed BPSK demodulator is presented. The whole demodulator is demonstrated both in simulations and experiments. Considerations on system-level design regarding the system performance yields an improved version of the demodulator, and then a design process for this improved demodulator. A compact integrated circuit (IC) design topology of the demodulator is proposed, as well as a multi-band demodulator based on this topology.; The proposed BPSK demodulator in this thesis is a candidate for current satellite communication systems, such as INMARSAT systems and GPS system, as those systems thirst for low-cost, compact and light-weight portable terminals. The other applications of this demodulator are in RFID system and next radio generation---digital radio system.