| The emergence of digital signal processors (DSP) for telecommunication and multimedia applications create the need for integrated, high-resolution analog-to-digital converters (ADC). However, the DSP system requires high accuracy, so an ADC must be at least as accurate as the precision of the overall DSP system.; Sigma Delta (SigmaDelta) modulation using oversampling is 1 type of ADC that achieves high resolution by removing out-band quantization noise. The purpose of this thesis is to implement a small, simple SigmaDelta converter in 0.18 mum CMOS technology using Cadence, electronic design automation (EDA) tools. This paper provides the detailed design of a first-order, noise shaping SigmaDelta modulator. First, the explanation of each component and the Simulink simulations of the SigmaDelta converter are presented. Then, the SigmaDelta converter is designed and verified with the Cadence software. The Cadence simulations show that the SigmaDelta converter can achieve 6-bit resolution for 1 MHz signal band, working at 500 MHz clock. Finally, the custom layout design of the first-order, noise shaping SigmaDelta modulator is presented.; To reduce the sampling rate of the output signals of the SigmaDelta converter, a decimator is required. This paper also presents the design, the performance, and the layout of a dual third-order, half-band decimator. |
