| Nowadays, along with the economic and technical progress, modern communication industry is playing a more and more important role in people's lives. The rapid growth of communication industry is benefiting and gradually changing our work, learning, and life styles. It is difficult to imagine what life will be like without smartphones, HDTVs, high-speed networks, and Wi-Fi hotspots. On the other hand, the ever-increasing users' demands force the modern communication systems to be faster, more portable, more reliable, and safer. As an indispensable and important part of modern communication systems, channel decoders are expected to be low-latency, low-complexity, low-error, and wiretap-free. However, developing channel decoders to meet those requirements is quite a struggle. Fortunately, VLSI digital signal processing techniques offer us great facilities to enable channel decoders to advance to new generations.;This thesis commits itself to the efficient VLSI implementation of low-latency low-complexity channel decoders. In order to make our approaches more applicable for variant real-time communication applications, formal design methodologies are proposed. Novel non-binary QC-LDPC decoders with efficient switch networks are presented. For the newly invented polar codes, a family of latency-reduced decoder architectures is also proposed. Comparisons with prior works have demonstrated that the proposed designs show advantages in both decoding throughput and hardware efficiency.;First, a novel design methodology to design low-complexity VLSI architectures for non-binary LDPC decoders is presented. By exploiting the intrinsic shifting and symmetry properties of non-binary quasi-cyclic LDPC (QC-LDPC) codes, significant reduction of memory size and routing complexity can be achieved. These unique features lead to two network-efficient decoder architectures for Class-I and Class-II non-binary QC-LDPC codes, respectively. Comparison results with the state-of-the-art designs show that for the code example of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save up to 70.6% hardware required by switch network, which demonstrates the efficiency of the proposed technique. The proposed design for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% switch network complexity reduction compared with conventional approaches. Furthermore, with the help of a generator for possible solution sequences, both forward and backward steps can be eliminated to offer processing convenience of check node unit (CNU) blocks. Results show that the proposed 32-ary (992, 496) rate-0.5 Class-II decoder can achieve 4.47 Mb/s decoding throughput.;Second, the low-latency sequential SC polar decoder is proposed based on the DFG analysis. The complete gate-level decoder architecture is proposed. The feedback part is proposed to generate control signals on-the-fly. The proposed design method is universal and can be employed to design the low-latency sequential SC polar decoder for any code-length. Compared with prior works, this design can achieve twice throughput with similar hardware consumption.;Third, in order to meet the requirements of high-throughput communication systems, both time-constrained (TC) and resource-constrained (RC) interleaved SC polar decoders are proposed. Analysis shows that the TC interleaved decoders can multiply the throughput and achieve much higher utilization. Also, the RC interleaved decoders can improve the decoding throughput while keeping the hardware complexity low. Compared with our pre-computation sequential polar decoder design, the RC 2-interleaved decoder given here can achieve 200% throughput with only 50% hardware consumption.;Finally, the decoder design issue of the newly proposed simplified SC (SSC) decoding algorithm for polar codes is investigated. Since the decoding latency for SSC algorithm changes with the choice of codes, a systematic way to determine the decoding latency is derived. By following a simple equation, we can calculate the decoding latency for any given polar code easily. A formal DFG-based design flow for the SSC decoder architecture is developed also. Furthermore, in order to always achieve a lower decoding latency than previous works, a novel pre-computation SSC decoder architecture is also proposed. A (1024, 512) decoder example is employed to demonstrated the advantages of the proposed approaches. |
