| Variable delay elements are one of the basic units in digital logic circuits to produce an output waveform similar to its input waveform, only delayed by a controllable amount of time. They are often used to manipulate the rising or falling edges of the clock or any other signal in digital systems, for example phase-locked-loops (PLLs) and delay-locked-loops (DLLs), which are crucial components in clock management circuits. In this project, we propose a new delay element in resistor-capacitor (RC) architecture and develop an analytical equation for the relationship of the output delay time and the control voltage. The proposed circuit exhibits improved delay characteristics over previously reported inverter-chains delay elements and could apply to any duty-cycle digital signals besides square clock waveforms. The chip was fabricated under TSMC 0.18u CMOS technology with the collaboration of Canadian Microelectronics Corporation (CMC). The maximum operation data rate could be up to 2Gbps. |
