| Digital processing of signals has become an attractive option in mixed-signal systems, such as digital communication and medical instrumentation. When the input signal has a wide dynamic range, the system throughput is often limited by the conversion rate of the high-resolution analog-to-digital converters (ADCs). Time-interleaving of ADCs is an attractive way to increase the overall conversion rate in a given technology while keeping the high resolution. However, mismatches among the interleaved ADCs generate undesired spectral components and can significantly degrade the signal-to-noise-and-distortion ratio (SNDR) of the system.; The mismatches among the time-interleaved ADCs are analyzed and simulated. Techniques to overcome the errors caused by (1) offset mismatch, (2) gain mismatch, (3) sample-time error, and (4) bandwidth mismatch among time-interleaved ADCs in high-speed digital communication systems are presented in this thesis. All the corrections are performed by digital signal processing blocks, which can scale to take advantage of evolving CMOS technologies. The digital calibration blocks are modified from the existing blocks in a digital communication system so that the hardware overhead is minimized. The offset and gain correction circuits are relatively simple. A front-rank S/H is not required, which allows many ADC channels to be time interleaved. The correction of sample-time errors and bandwidth limiting can be performed using a modified version of the equalizer, which is an existing block in most digital communication receivers. Hence, the offset, gain, sample-time, and bandwidth mismatches can be corrected with low hardware overhead. Simulations are presented that show that the mismatches are corrected by the adaptive loops. |
