Etude en vue d'adapter la methodologie IBIS a la simulation interne des circuits integres (French text)

This study puts forward a new modeling technique, named GIS (I/O Buffer Information Specification), allowing the electric behavior emulation of the active structures found in integrated circuits (ICs). It relies on the adaptation of the principles sustained by IBIS [10], a largely accepted methodology in the field of printed circuits allowing the validation of the integrity of the electric signals transiting between the ICs.; The GIS (Gate Information Specification) modeling states as an hypothesis that the activation speed of the transistors are insensitive to the parasitic load found at the output. Thus by time modulating the DC characteristics of the transistors by switching coefficients representing the respective activation state, an empirical model is obtained. This model, which allows the emulation of the output electrical behavior in response to any complexity load, account for all submicronic effects such as: short-circuit current, input-output coupling capacitance (Miller capacitance) and also for the carriers saturation effects. The use of the behavioral Spice model will be useful to demonstrate the efficiency of the proposed GIS mechanism without having to develop a specialized simulator being able to accept such models.; The efficiency of GIS has been validated over a large range of testbenches representing diverse situations found in the IC world. GIS was tested on signals between memories elements found inside an IC, in order to validate the integrity of their noise margins which can be affected by electromagnetic interference problems. Unlike the analytic approach, the GIS modeling is in fact far more attractive in light of the increased complexity of physical phenomena's brought by technological advances due to the fact that it is completely dissociated from the problem of modeling interconnects.