Computational model for re-entrant multiple hardware threads

One of the challenges faced by the embedded and real-time system designers is to meet the system requirements rapidly and with low cost. An ideal way to meet these requirements is to use commercial off-the shelf components (COTS). Creating COTS components that are reusable in a wide range of applications is difficult. Custom components made available by reconfigurable devices typically achieve higher performance than COTS components but at higher development cost. However, a large obstacle in realizing the potential advantages of reconfigurable components is that programming these devices is still difficult. A high level-programming model is needed that abstracts the FPGA and CPU components available in the hybrid chips. The multi-threaded programming model has been developed in this thesis as a convenient way to describe embedded applications and has many ideal properties that may allow FPGA resources to be more fully utilized. This report will answer the question of how to map a threaded programming model onto a computational model for modern FPGAs.