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Enhancing Lifetime Reliability Of Chip Multiprocessors Through 3D Resource Sharing

Posted on:2014-11-13Degree:M.SType:Thesis
University:University of California, San DiegoCandidate:Strikos, NikolaosFull Text:PDF
GTID:2458390005497305Subject:Computer Science
Abstract/Summary:
3D TSV technologies enable higher degrees of device integration and interconnection, but they also pose many new design challenges. Lifetime reliability has already become a first-class design constraint as CMOS processes approach the nanometer scale, and, combined with 3D integration, is threatened by another major hit as thermal issues are yet to be effectively solved. Commercial adoption of the next-generation, logic-on-logic 3D designs will be delayed unless manufacturers can guarantee that, in addition to superior performance, their 3D-enabled products meet the expected lifetime reliability goals as well.;In this work we propose taking advantage of prior work in 3D die stacking technology to allow vertically stacked cores to communicate with each other and allow their resources, defective or not, to be shared. With resource sharing, a defective unit, or part of it, can be decomissioned and the core it belongs to be revived by borrowing a unit of the same type from a vertically adjacent non-faulty core. Our approach centers around two techniques that, based on resource pooling, enhance the lifetime reliability of the multi-core system by dynamically adapting the core resources without redundancy or performance loss. With Core Resuscitation, fine-grained reconfiguration around faulty components allows us to prevent decommissioning a whole core because a single resource is faulty. With Resource Salvaging, functioning units of decomissioned cores can be assigned to the surviving cores to improve their performance and expected lifetime. Our results show that resource pooling is unique in boosting both performance and lifetime reliability at the same time.
Keywords/Search Tags:Lifetime, Resource, Performance
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