| Nanoimprint Lithography is being explored by the semiconductor industries for future high volume fabrication of silicon chips, memory devices and patterned media. Nanolithography and Microlithography has played pivotal role in the field of manufacturing microchips and integrated circuits in semiconductor devices. There is an urge to investigate Nanoimprint lithography, a high-throughput, low-cost and nonconventional lithographic method. Thermal management is a critical area that is necessary to be administrated. As recent advancements are being observed in the field of electronic packaging for thermal optimization, likewise steps are also important in this fabrication process.;This process involves a heat that is generated by various means like UV and high pressure. This heat results in creating a temperature gradient over the silicon wafer. The temperature profile in turn introduces thermal stress in the wafer, as little increase in temperature will have adverse effect on the quality of the product. This proves to be an important factor for aligning a silicon wafer over one another. On a single wafer multiple chips are patterned and thus the heat produced by adjacent chips also adds up to this problem. So we need to discuss various aspects of this heat generation and find a way out to have a optimize solution of this problem. Thus taking inspiration from the above problems, the simulations were computed to get the desired results. The basic set up comprises of the wafer chuck, wafer, template and template chuck with designated materials. Now a heat source is created in order to resemble the UV exposure on the wafer with the dimensions matching the size of a chip. These set up is used for computing steady state and transient simulation to obtain the temperature profile over the wafer and to get optimal results. The simulations were based on analyzing the temperature dependency on power density while keeping the total dose constant. Based on these temperature results other simulations were carried. The structural analysis to find stress was computed using body temperature as loading. The stress results show the equivalent (von-Misses) stress in the wafer. Moreover the writing also discusses the optimal pattern in which the exposures should be carried in multi-chip exposure. |
