Performance Evaluation Of Cache Replacement Policy For CMP

As the semiconductor industry heads into the nanometer era, more and more transistors are incorporated into the integrated circuits. Compared with the uniprocessor, Chip Multi-Processor (CMP), due to its obvious advantages in system throughput, power efficiency, and reliability, has been accepted both by the commerce market and academia as the mainstream architecture. On the CMP platform, the slow increment of the off-chip bandwidth, which is too slow to catch up with the increment of the number of cores, together with the diverse workload characteristics make the Memory Wall problem more and more seriously. The organization and optimization of the chip memory system, especially the last level cache, are becoming the crucial factor of the CMP's performance.Cache replacement has always been one of the most important components in the cache management mechanism. The model of cache replacement is an effective and practical tool for the cache optimization. However, current cache optimization researches mainly focus on the policies and are lack of qualitative analyzing. This paper tries to modeling the cache replacement, and the main contributions are as follows:1 A model for cache dynamic insertion replacement is present. In the CMP, the classic cache replacement LRU gradually loses its performance due to the cache dead block problem caused by high cache associativity. As a result, dynamic insertion policy, which can effectively solve such problems of LRU, has received much more attention. However, current research mainly focuses on the replacement policy, while there is few works on the quantitative analyzing of the replacement policies. This paper presents a new analytical cache model for cache dynamic insertion replacement. The model inputs the application's reuse distance information and employs the Markov process to predict the miss rate of each circular sequence, and finally get the application's miss rate through multiple iterations to choose the optimal dynamic policy for the application.2 To accelerate the model calculation, three accelerating methods are proposed. Recently proposed cache models, as well as our model, are too complex to calculate. After analyzing the complexity of the model, two theorems of the dynamic insertion policy is demonstrated and used to accelerate the speed of the model. The state space of Markov process is compressed by dynamic programming. When calculating the total miss rate, 3-max strategy is adopted. Through these accelerating methods, the speed of the model is greatly improved, and the model's complexity is reduced to polynomial from exponential.3 The evaluation and validation of the dynamic insertion policy is performed against the Simics, a cycle accurate execution driven simulator, on the SPEC2006 benchmark. The simulation results, in which the average error is -0.4% and the max error is only 6.99%, reveal that the model is always able to give an accurate miss rate prediction for different insertion policies.