Integration and characterization of silicon nanowire field effect devices

The ability to engineer materials at the nanoscale utilizing a combination of controlled nanomaterial synthesis and self-assembly methods offers the potential to create new electronic devices with improved performance and functionality. Semiconductor nanowires (NWs) provide an ability to utilize the fundamental electronic building blocks that have been developed over a half-century of semiconductor technology and flexibility to integrate a wide choice of materials on a silicon platform. Moreover, semiconductor NWs could be used as an excellent model system for answering fundamental questions related to semiconductor device process integration and electrical transport at the nanoscale. In this thesis, my work on integration and characterization of silicon nanowire (SiNW) field effect (FET) devices is presented. This work provides a basis for understanding process integration and electrical transport in ultra-scaled devices.;First, we describe the synthesis of SiNWs using an Au-catalyzed vapor-liquid-solid (VLS) growth technique. Transmission electron microscopy (TEM) studies indicate that the SiNWs have single crystal cores that are sheathed with a 2--3 nm thin amorphous native oxide. We developed a general integration process to electrically address individual SiNWs in a global-back-gated test structure with four top-side electrodes. The electrical measurement results of four-point resistance and gate-dependent conductance demonstrate that trimethylboron and phosphine can be used as a source of boron and phosphorus for in-situ p- and n-type doping of SiNWs during VLS growth, respectively.;Second, we utilized thermal oxidation of SiNWs to form Si core/SiO 2 shell NW for fabricating top-gated SiNW FET devices. Structural characterization on thermally-oxidized SiNWs shows that the interface between the Si core and SiO2 shell is smooth and the SiO2 shell is uniform along the length of the NW. The field effect measurements show that thermally-grown SiO2 shell is suitable for use as the gate dielectric in the top-gated SiNW FET device structure, which has better device properties and stronger gate modulation than the global-back-gated test structure. Furthermore, the large hysteresis commonly observed in the subthreshold properties of the global-back-gated test structure is significantly suppressed in the top-gated FET structure. Both p- and n-channel top-gated SiNW FET devices were demonstrated, which facilitates fabrication of complementary SiNW FETs.;Third, we successfully synthesized axially-doped n+-p --n+ SiNWs by sequential introduction of n- and p-type dopant gases during VLS. TEM studies show that the length of each segment is well controlled and the transition between n+ and p - is sharp. The characteristics of FETs fabricated using these SiNWs resemble conventional n-channel MOSFETs, which indicates inversion-mode operation with dominant electron transport. Control samples with different S/D configurations fabricated using a global-back-gated FET structure confirm that there is no deleterious n-type overcoating along the p- segment. These results demonstrate the potential to use SiNWs for future nanoelectronic device application or as a model system by engineering the doping profile during VLS growth and taking advantage of various gating structures.