| During the last few decades, academia and industry have invested considerable effort in research on physical design for VLSI. The growing size of ICs makes the development of CAD software a challenging process. The number of transistors in a circuit is increasing and the interconnect delay is increasing to dominate the circuit performance. This paper discusses some important problems regarding these new challenges in physical synthesis. Placement with mixed-size modules, timing optimization by incremental placement, timing criticality problem and floorplanning for routability and design uncertainty are addressed in this work.; In the first chapter, an incremental timing-driven placement algorithm is presented. We introduce a path-based analytical approach. Our algorithm is an incremental approach, which does not change the placement drastically but achieves timing optimization.; In the second chapter, we discuss the timing criticality problem for timing optimization. We propose an algorithm that considers all paths and finds the most timing critical nets. In timing optimization, identifying the tinning critical portion is a very important problem.; In the third chapter, we give a placement algorithm for mixed-size modules. Placing large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. We present a global placement method that combines a hierarchical simulated annealing floorplanning method with a partitioning-based global placement technique.; In the fourth chapter, we present a force-directed floorplanning algorithm. Our algorithm gives the shortest wire length; meets performance constraints and considers design uncertainty. |
