Circuit and physical design for system-level power and performance

This dissertation first study automatic synthesis of power supply network with embedded sleep transistors. Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we formulate the placement of sleep transistors in P/G networks as a min-area sleep transistor insertion (and sizing) problem. Our theoretical analysis reveals the conditions to achieve optimal placement of sleep transistors applicable to any P/G network topology. We also study the placement of sleep transistors under a sizable P/G network, and formulate it as a simultaneous sleep transistor insertion and P/C network sizing problem. We reveal the conditions to achieve optimum solution for the sleep transistor insertion problem, which is applicable to any P/G network topology too. Our study shows that these optimal solutions are non-unique, which provides design freedom to consider other design metrics such as routing congestion.; We then propose a stacked power supply which consists of an off-chip pulse width modulation (PWM) buck converter to supply majority of the power and a distributed array of on-chip pulse frequency modulation (PFM) buck converters to obtain supply voltage levels that may be individually controlled for different regions over the chip. Experiments show that the proposed stacked power supply over a realistic Pentium pro model has over 81% power efficiency in voltage conversion. The output voltage ripples across all voltage domains are less than 5.0%.; The last part of the dissertation studies microarchitecture and floorplanning co-optimization. We build a unified throughput model parameterized for pipelined global interconnects and microarchitecture configurations based on the TPWL method, and apply this model to efficiently explore over one million microarchitecture configurations and corresponding floorplan variations. We obtain microarchitecture configurations and floorplans with throughput 26.9% better than manually chosen microarchitecture followed by automatic floorplanning in the literature.