| The increment inverse operation and inverse operation have been observed to be useful in computations involving signal processing. Increment inverse operation performs an increment on a floating-point number N and to generate the result R where R = (1 + N). This R is then inversed, that is output O = 1/ R is computed and normalized.; Increment Inverse operation would have been easy task while computing in an integer or a plain binary number system. Many design issues such as denormalizing, rounding, normalizing, overflow arise when floating-point numbers are involved.; The hardware structure is optimized to perform the computation with binary floating-point numbers. The specialized hardware could be utilized for speeding up the circuit when real-time operations are involved. This hardware could be utilized in computations where division is realized with addition and multiplication hardware.; The thesis presents a floating-point module that performs an increment inverse operation in real-time. The bit-widths of mantissa and exponent are made scalable so that it could be used with the standard IEEE 32 bit format or a format more specific to the required hardware. |
