Bulk operation and data coloring for multiprocessor programmability

With ubiquitous multi-core architectures, a major challenge is how to effectively use these machines. Writing parallel programs is usually very complex and error-prone. Hence, improving the programmability of parallel computer systems is a massive problem for much of our field. We believe that architecture support plays a key role in making parallel programming accessible to the masses. This thesis focuses on simple and flexible mechanisms that are used to improve the programmability of shared-memory multiprocessors.; This thesis makes two main contributions. The first contribution is efficient coarse-grain operation of multiprocessors. This allows groups of dynamic instructions to behave as a unit in a multiprocessor system. The main idea in making coarse-grain operations efficient is to hash-encode a thread's access information in a concise signature, and then support signature operations that efficiently process sets of addresses in bulk. These operations are inexact but correct, and provide substantial conceptual and implementation simplicity. We show how to use these operations to simplify support for features that improve programmability. Specifically, we discuss designs for Transactional Memory, Thread-Level Speculation and high-performance sequential consistency. We also suggest other possible uses of bulk operations to illustrate its versatility.; The second contribution of this thesis is architecture support and programming model for a data-centric approach to thread synchronization. In Data-Centric Synchronization (DCS), the programmer uses local reasoning to assign synchronization constraints to data. Based on these, the system automatically infers critical sections and inserts synchronization operations.