Modeling, characterizing, and mitigating the impact of process variations on the energy-efficiency of chip-multiprocessors

Semiconductor manufacturing process variations are worsening with continued reduction in transistor feature sizes. However, technology scaling is the engine driving the semiconductor industry and must continue. When variations worsen to the point that they can no longer be addressed solely at the device and circuit levels, the next logical step is to develop variation-tolerant microarchitectures.;This thesis presents research on modeling, characterizing, and mitigating the impact of process variations on the energy-efficiency of modern chip-multiprocessors. New models are developed for how variations impact chip-multiprocessor power and performance at a variety of granularities, from within a single core to among dies in a speed bin. These numerical models, fit to HSPICE data, achieve orders of magnitude lower error than the analytical models traditionally used in microarchitecture-level research.;These models are used to drive the motivation and evaluation of two new schemes for reclaiming some of the energy-efficiency that is lost to process variations, both predicated on addressing variation in static power. Variation-aware level selection (VALS) works in the context of dynamic voltage/frequency scaling (DVFS), a popular method for improving energy-efficiency. In fine-grained DVFS implementations, the chip is divided into multiple voltage/frequency islands, each with its own power grid and clock network. Because every VFI in a given speed bin runs with the same set of voltage/frequency levels, leaky VFIs are inherently less energy-efficient than their less leaky counterparts. VALS biases VFIs towards higher or lower voltage/frequency levels based on their level of leakage, shifting work from energy-inefficient, leaky VFIs to energy-efficient, less leaky ones.;Test-time voltage selection (TTVS) is a new method for integrating DVFS with adaptive body biasing (ABB). When ABB and voltage scaling are both implemented, a given frequency target can be achieved with many different supply voltage/body bias combinations, each with its own power consumption. The energy per switching event is largely unaffected by process variations, so leakage power determines which of the supply voltage/body bias combinations will yield the lowest power. TTVS uses a design characterization to create functions mapping a test-time measurement of a VFI's leakage power to its supply voltage for a given frequency level. By using these mappings during test, each VFI can be assigned a supply voltage much closer to optimal than with naive schemes.