| As manufacturers go into volume production with 90nm designs and below, the defect diagnosis has become a challenge in the initial yield ramp. In this thesis we propose several techniques to improve the defect diagnosis accuracy, resolution and run time.; We first introduce several techniques to enhance location based logic defect diagnosis. In the proposed method, we analyze the relationship of logic failure locations and collapse multiple logic failure locations into single defects. In this way, we can not only identify defect type but also improve diagnosis accuracy and resolution.; In order to further improve diagnosis accuracy and resolution, we introduce a new method to diagnose bridge defects by using physical information. Circuit behavior in the presence of bridge defects is affected by three factors: bridge resistance, drive strength of bridged signals and the threshold voltages of down-stream gates. Current bridge defect diagnosis methods either ignore all of these factors or consider drive strengths and/or threshold voltages only. So the diagnosis results from current procedures may not be as accurate as possible. In the proposed method, we take all three factors into account. Experiments demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution.; Besides bridge defect, we also present a new method to diagnose interconnect open defect by using physical information. Circuit behavior in the presence of interconnect open defects is affected by four major factors: the capacitances between the floating node and its neighboring nodes, the capacitances inside down-stream gates, initial trapped charge, and the threshold voltages of down-stream gates. In the proposed method, we take all these factors into account. This overcomes the drawback that only a subset of factors is considered by previous methods.; Finally we present a method of passing pattern selection to speed up effect-cause defect diagnosis. The proposed method only selects a subset of the passing patterns to simulate based on the clock pulsed under each test pattern. The experimental results conducted on industry circuits validate the effectiveness of the proposed method. |
