Source re-coding to create parallel and flexible MPSoC models for embedded system design and exploration

To overcome the complexity in Multi-Processor System-on-Chip (MPSoC) design, researchers have developed sophisticated methodologies and design flows that significantly reduce the development time through automation. Given a suitable input SoC model, Electronic System Level (ESL) tools today are effective in generating efficient implementations. However, while much work has focused on synthesis and exploration tools, little has been done to support the designer in writing and rewriting MPSoC models. In fact, our studies on industrial size examples have shown that about 90% of the system design time is spent on coding and re-coding of System Level Description Language (SLDL) models, even in the presence of algorithms given in the form of C code. Since the quality of the design model has tremendous impact on the cost and quality of the resulting system implementation, creating and optimizing the model is a critical and necessary task toward successful SoC design.;Re-using readily available C algorithms as a starting point of the SoC design can speed-up the SoC design process. However, readily available reference C codes are not conducive for system synthesis as they lack the necessary characteristics such as parallelism, structural hierarchy, analyzability and synthesizeability. The reference C codes lack proper isolation of computation and communication, lack parallelism, contain intractable pointers and unanalyzable control structures, which render today's ESL tools ineffective. Reusing these C sources for creating SoC models requires significant non-trivial re-coding, which could result in sub-optimal models if not done correctly. The lack of sufficient automation help to create these models requires that designer manually implement this re-coding, which is very time-consuming and error prone.;This thesis focuses on this automation-gap, which is widely prevalent across many system-level design flows today. To overcome this automation gap, we present our novel "Recoding" approach, which efficiently combines the automation with the designer's application-specific knowledge. In this approach, the overall task of creating the SoC model from C reference code is achieved through iterative application of several recoding transformations. In this thesis, we present several source-level code transformations to create a suitable SoC model. Our code transformations address aspects such as separating computation and communication, code parallelization, code partitioning, and code restructuring.;We also present the working implementation of the recoding approach in the form of an interactive source re-coder, which integrates static analysis and code transformation tools into an editor, to assist the designer in tedious modeling and optimization tasks. This recoding approach to create efficient SoC models allows the designer to use her/his limited modeling time efficiently, and makes the whole approach feasible on real-life source codes.;Experiments using our source re-coder prove the feasibility and effectiveness of this interactive approach, which utilizes the designer's knowledge for decision making and automation for re-coding. The design explorations conducted on the models created using our source re-coder clearly demonstrate the effectiveness of our approach. The two orders of magnitude productivity gains achieved through our source re-coder compared to manual re-coding significantly reduce the overall system design time. This automation not only helps the designer in creating models faster, but also enable the designers to quickly realize different models and compare the trade-offs and benefits of each type of model. By having control over the type and scope of the transformation, the designer can use these generic transformations to create models acceptable to the design flow and most suitable for the underlying platform.