| As the microelectronic industry evolve, the need for more efficient communication networks is important to the success of new System on Chip (SoC) designs. These systems are complex. To manage that complexity, they must be divided into multiple blocks: processors, memories, I/O controllers, specialized hardware blocks, etc. We present an FPGA prototype implementation of a Rotator-on-Chip (RoC), a simple and scalable novel network-on-chip based on the token-ring concept developed in collaboration with STMicroelectronics in Ottawa. The reported prototype design is generic with respect to the number of nodes, data width and address space. Nowadays, several architectures and some commercial products exist, but NoC implementation results are scarce. Our architecture differs from others in the literature, but still uses important basic concepts of NoCs. We first summarize these concepts and review related works. The RoC functionality and the details of our FPGA validation platform are presented. Then we report synthesis results showing a less-than-quadratic area growth with respect to the number of nodes, yet with a quasi-linear aggregate bandwidth growth. For 8 nodes or less, hardware complexity of the RoC is lower than the mesh implementation. For 12 nodes and beyond, the RoC consumes more FPGA resources than a mesh. However, the RoC can support simultaneously all possible one-to-one connections between source and destination nodes, which is not the case for the mesh. In terms of latency, the RoC latency is shown to be 3.7 times lower than that of a mesh. The RoC implementation approximates the performance of a crossbar but uses much less area. The slice utilization is less than 25% of those available on a Xilinx VP100 for a 16 node version of the RoC, supporting an aggregate bandwidth of about 6 GB/s. The implementation has been validated by simulations and implemented on a FPGA development board. |
