| The ability to scale CMOS while keeping power density roughly constant represents a significant limitation to meeting late stage International Technology Roadmap for Semiconductors (ITRS)1 specifications. Neuronal computational systems provide an alternative to binary systems, and by design are extremely power efficient due to massive parallelism. One way to achieve the high level of interconnectivity and low power density seen in the nervous system is to use amorphous silicon devices in the interconnect layers of a CMOS stack. The aim of this work is to correlate amorphous silicon TFT electrical characteristics to physical characterization results. Device materials and processing conditions were varied to find trends in the extracted parameters. An optimum in the experiment space was found, and the device was modeled using AIM-SPICE. An example neuromorphic circuit was simulated using this model, which showed low power dissipation. The feasibility of using amorphous silicon in neuromorphic applications is thus demonstrated. |
