Low frequency noise as a characterization and reliability tool for the evaluation of advanced MOSFETs

The continued scaling of MOSFET feature sizes, including the gate area, has been the major approach of the integrated circuits industry to achieve increases in speed and density for the past 40 years. This reduction in the gate area leads to several very challenging problems and even potential roadblocks, due to the fundamental limits imposed by the unbreakable laws of physics. One of these is the inevitable increase in device noise levels, which has significant impact on the device performance.;In this thesis, noise in these advanced MOSFETs is characterized, and used for evaluating alternative technologies on both of these fundamental requirements. For the first requirement, noise characterization offers a powerful yet simple way to evaluate the passivity of the new semiconductor-dielectric interface. Noise behavior subject to various bias and gate scaling reveals device transport mechanisms that are otherwise unseen in measured I-V curves. For the second requirement, the noise behavior of the candidate devices under stress tests often manifest damage earlier than detectable by more conventional methods, and the manner of noise degradation adds evidence to the suspected transport mechanisms.;Advanced MOSFET devices that were characterized in this work covered various types, and include one where silicon was still used as the channel material, but with a hi-kappa dielectric (SiSiHfON), another where germanium was used as the channel material coupled with a hi-kappa dielectric (Ge-HfO 2), and a third where 1-D carrier transport was utilized with carbon nanotubes as the channel material (CNTFETs).;The advanced bulk MOSFETs (Si-HfSiON and Ge-HfO2) were shown in this work to have higher magnitudes of 1/f noise than conventional Si-SiO 2 MOSFETs in agreement with expectations due to higher interface trap densities. It was also shown that these advanced bulk devices have similar bias and scaling dependence of the noise to that of conventional Si-SiO 2 MOSFETs, giving evidence that the mechanisms for noise are similar. Under hot-carrier stress, it was found that the noise degradation of these devices eventually saturated, while the threshold voltage degradation did not for the period of time tested, giving evidence that the main contribution to the voltage shifts in these devices is due to mobile charge migration in the oxide, in agreement with the observed hysteresis and threshold voltage instabilities.;Due to the limitations of continued scaling, research has started to focus on alternative materials to the Si-SiO2 combination in conventional MOSFETs. These alternative material combinations must meet two fundamental requirements in order to be seriously considered as potential replacements for conventional silicon technology. The first is that the alternative material devices must exceed several operating benchmarks of conventional silicon devices, and the second is that it must also maintain these advantages throughout their commercially useful lifetime.;For CNTFETs, it was shown that despite the transport advantages of 1-D CNTs, these devices have much higher noise levels than conventional CMOS devices and hot-carrier stress led to degradation comparable to conventional Si-SiO 2 MOSFETs, giving evidence that a source of 1/f noise in CNTFETs is the underlying oxide. These results emphasize that reliability studies of CNTFETs must not be ignored, if the technology is to become a viable alternative for CMOS.