Placement techniques for the physical synthesis of nanometer-scale integrated circuits

Placement is a critical component in the physical synthesis of nanometer-scale integrated circuits. Placement of circuit modules determines to a large extent interconnect length and routing resource demand. Interconnect length has a direct impact on the interconnect delay, which has become the determining factor of circuit performance in nanometer-scale process technology. In addition, interconnect length has a direct impact on the circuit power. Hence, the quality of the placement significantly affects the ability of a physical synthesis tool or designer to achieve design closure.;In this work, efficient and high quality placement techniques have been developed for the physical synthesis of multi-million gate integrated circuits in the nanometer regime. The focus of these techniques are: (a) global placement and legalization of mixed-size circuits to minimize interconnect length, circuit power and routing resource demand, and (b) incremental physical synthesis via integrated timing optimization and placement to achieve timing closure.;The effectiveness of the techniques is demonstrated by: (a) comparing them with existing approaches that perform integrated circuit placement, and (b) embedding them within a state-of-the-art industrial physical synthesis tool that is used in the design of high performance integrated circuits in the 65nm and 45nm process technology nodes.