Compact modeling of amorphous silicon thin film transistors

Amorphous silicon thin film transistors (a-Si:H TFT) are being used in a wide variety of applications such as image sensors, radiation detectors and large area electronic printing, as well as for their conventional use in liquid crystal displays. The stringent performance specifications of such applications necessitate the development of accurate compact models for computer simulation during their design. A number of analytical compact models based on the physics of a-Si:H TFT operation have been developed for circuit simulators. Regrettably, most of the known models are unable to capture time and frequency dependent effects such as threshold voltage shift, which are of critical importance for circuit designers. Additionally, these models suffer from deficiencies such as: The contact resistance does not scale with the device width, the intrinsic capacitance does not conserve charge and the leakage current is miscalculated.;This thesis explores an alternative approach of modeling the a-Si:H TFT with the industry standard Berkeley Short-channel IGFET Model (BSIM3) compact model successfully capturing the measured current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a n-channel a-Si:H TFT in all operating regions. To represent the gate bias-induced threshold voltage degradation a novel time dependent circuit model is incorporated inside the Spice 3.0 circuit simulator to obtain a composite a-Si:H TFT BSIM3 model. The major finding of this thesis is the identification of the localization of the threshold voltage degradation phenomenon using a set of new measurement experiments. Additionally, a graphical model parameter extraction and optimization program has been developed that compares the modeled with the measured I-V and C-V curves. Finally, to validate the a-Si:H TFT BSIM3 composite model, amorphous silicon static and dynamic programmable logic arrays (PLA's) have been designed and fabricated on flexible stainless steel. By comparing the simulations and measured test results of both PLA's this thesis favors the dynamic logic style in the design of flexible a-Si:H logic circuits, which are faster and dissipate lower total power than their static counterparts.