| Embedded systems are application specific, and have strict timing and power constraints. Designing high performance and low power embedded systems with various constraints and limited resources has become an important research problem. In this thesis, we investigate the challenging issues in designing compiler-assisted techniques for solving high performance and low power optimization problems in embedded systems. Our contributions are as follows.;First, we develop a technique called "REALM" to reduce the number of memory accesses for DSP applications with loops. In the loop kernels, one important characteristic is that the same memory location is repeatedly accessed by different memory operations over multiple loop iterations. We solve the problem by replacing redundant memory operations with register operations.;Second, as embedded systems have a limited number of registers, we propose a register allocation and instruction scheduling technique to improve the "REALM" technique with register constraints. For the register operations generated by the "REALM" technique, we analyze their data dependencies for instruction scheduling, and build up a register-matching graph model to find available physical registers that can be allocated to the operands of the register operations.;Third, we propose a novel leakage-aware modulo scheduling technique that helps hardware-based leakage control schemes to achieve leakage power savings for embedded VLIW processors. We also consider transition time and power overhead in our technique, and discuss the trade-off between leakage savings and performance penalties.;Fourth, we propose to reduce the peak temperature of the on-chip memory subsystem. Most embedded systems adopt a hybrid memory architecture, which contains both hardware-managed cache and software-managed scratchpad memory (SPM). However, both cache and SPM have become hot spots, as they are the most frequently accessed on-chip components. We propose a temperature-aware data allocation technique to explore such hybrid architecture to jointly optimize performance and peak temperature. |
