Design and evaluation of an output CPU-DRAM interconnect

Four decades ago Amdahl proposed a set of rules of thumb for computer architects that have withstood the test of time. One such rule of thumb is that a balanced computing system should be capable of providing one byte of memory and one byte per second of memory bandwidth for each instruction per second of computation. Building balanced computing systems in the multicore era with hundreds of processing cores per die is challenging because of the pin limitations and poor scalability of bandwidth and memory capacity with off-chip electrical interconnects between the CPU and memory subsystem.We propose using Wavelength Division Multiplexing (WDM)-based opticaLinterconnects between the CPU and the memory subsystem to overcome the problems of pin limitations and provide both high bandwidth and high memory capacity simultaneously. We make use of concepts studied widely by long distance optical networks such as dynamic wavelength allocation and bandwidth management in our design. The main contributions of this thesis are (a) A prototype design of an optical interconnect for CPU-DRAM interface without any modifications to commodity DRAM devices. (b) A frame-based protocol for interfacing CPU and DRAM with WDM-based optical interconnects. (c) Algorithms for dynamically allocating optical resources for better utilization and more concurrent operations. We show that significant improvements in memory bandwidth and memory capacity can be achieved, by exploiting the wavelength domain concurrency offered by WDM-based interconnects.