| This work studies the electromigration in lead-free solder joints of an encapsulated copper post wafer level package by finite element modeling. As the electronics industry continues to push for high performance and miniaturization of electronic devices, the demand for high current density may cause electromigration failures in integrated circuits (IC) interconnects and in solder bumps of an IC package. For a standard wafer level package with under bump metallization (UBM) layer structure, it was found that the electromigration occurs inside the solder which is adjacent to UBM layer on silicon side. A recently developed copper post wafer level package shifts the electromigration failure from the silicon side to the PCB side, where the maximum current crowding takes place. In order to solve this problem, a new line-to-bump trace structural design at PCB side is proposed. Two new structural designs are considered in a full 3-D finite element model. Coupled electro-thermal multiphysics analysis is performed to solve electrical and thermal fields simultaneously. The ionic flux from electron wind and thermal response is calculated based on finite element solutions. The divergence of the total flux, which is the sum of the divergence of electromigration and thermomigration, is extracted at the critical locations in solder joints. Results show that the new proposed design structures can reduce the maximum current density by 19%, and the divergence of the total ionic flux by 42%. Thermal gradient is very small in solder joints, therefore, the main driving force for electromigration failures comes from current density. The finite element results on mesh dependency are discussed and relatively consistent results are obtained based on different mesh schemes. |
