Continuous compensation of binary-weighted DAC nonlinearities in bandpass delta-sigma modulators

This thesis introduces and discusses the implementation of a novel calibration technique to compensate for DAC element mismatches in bandpass multibit delta-sigma (DeltaSigma) modulators. The compensation is accomplished in the digital domain using the output bitstream of the DeltaSigma modulator; only a minor modification to the analog portion of the DeltaSigma modulator loop is needed. The technique is compatible with binary weighted element DACs and the storage requirements for the calibrated coefficients increases only linearly with the number of quantizer bits. The calibration is performed without breaking the loop, which allows continuous tracking of environmental drifts. Furthermore, the proposed technique is shown to be also applicable to lowpass DeltaSigma modulators with minor modifications to the system.;Simulation results show a peak signal to noise ratio (SNR) of 73.9 dB after calibration for a DAC with 1% mismatches, a sinusoid input signal near 1/4 of the sampling frequency and an oversampling ratio of 14. This 73.9 dB peak SNR result represents a 26 dB improvement over the non-calibrated case and it is only 0.4 dB lower than an ideal-DAC case.;The proposed compensation technique is applied to a fourth-order DeltaSigma modulator fabricated in 0.13 mum CMOS. The peak SNR of the tested chip, without compensation, is measured at 57.3 dB. With the implemented compensation technique, the peak SNR, increases to 64.5 dB. The peak SNR after calibration drops by 1.8 dB when severe mismatch is forced on the DAC elements while the same mismatch causes the SNR to drop by 10.1 dB if no calibration is used.