| In modern integrated circuits, aggressive device scaling, higher operating frequencies and increased circuit complexity have caused an increase in current and power needs while decrease in voltage levels. Consequently, power integrity design and analysis presents a major challenge in modern semiconductor designs and systems.;In this thesis, parallel simulation methods based on waveform relaxation techniques have been developed for fast and efficient power distribution network analysis and design. For this purpose, an efficient parallel algorithm for transient analysis of on-chip power distribution networks (PDNs) is proposed. Parallel Gauss-Seidel waveform relaxation (GS-WR) and enhanced pipelining techniques have been developed for improving the speed-up of the parallel algorithm proposed.;Also, sensitivity analysis of power distribution networks is addressed in this thesis. A novel parallel algorithm for fast sensitivity analysis, employing waveform relaxation techniques has been developed. The proposed parallel algorithm scales well with the increasing number of processors. Several numerical examples have been considered to demonstrate the accuracy, efficiency and speed up of the proposed algorithms.;The primary problem with the analysis of on-chip power distribution networks (PDNs) is their large size. Most conventional circuit simulation techniques prove to be inadequate for analysis of a network of this size. This warrants development of new simulation methodology adapted to handling large problem size. Furthermore, in recent years, parallel platforms are emerging as a powerful computation medium promising unprecedented processing ability in least possible time. Also, recently waveform relaxation (WR) techniques have been proposed for efficient analysis of power distribution networks on serial platforms. The waveform relaxation techniques can be very easily parallelized to provide fast scalable parallel algorithms for power grid analysis. |
