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Convertisseur analogique-numerique neuromimetique de basse consommation d'energie pour les biocapteurs

Posted on:2010-04-09Degree:M.Sc.AType:Thesis
University:Ecole Polytechnique, Montreal (Canada)Candidate:Ait Yakoub, My El MustaphaFull Text:PDF
GTID:2441390002987281Subject:Engineering
Abstract/Summary:
Analog-to-digital converters (ADC) play a major role in electronic circuits particularly in implementing biosensors. Various architectures for ADCs are differentiated by parameters such as; (i) speed of operation, (ii) precision, and (iii) energy consumption. Although the research domain related to ADCs is still very active, the state-of-the-art low-power designs do not have the needed low power consumption of nanowatts. Our objective aims to design and implement ADCs dedicated to realize sensors with low power consumption. They could be used with implantable sensors and Near-Infrared Spectrometry (NIRS) which is used to measure the brain activity of patients at the cortex level. The cited wearable NIRS biomedical system requires ADCs with particular specifications such as: (i) low power dissipation in nanowatt range for long-last operation necessary for multichannel systems, (ii) small area to be integrated in a system-on-chip (SoC) devices, (iii) medium resolution of 7 to 8 bits, and (iv) good linearity (DNL ≤ 0.5 LSB and INL ≤ 0.5 LSB) to reproduce the input signal in a reliable binary format.;We propose a neuromimetic ADC based on [R.Raut and Zheng (2005)], so called Neuron Cell ADC (NC-ADC). It comprises the morphology and the bioelectric properties of neurons. In particular, the architecture inherits the electrically excitable nature of neurons, and their primary function to transmit and spread the nerve pulses with the same amplitude or actions potentials (APs). The front-end of the proposed structure operates on the same principles as the classical dual-slope integrating ADC. However, the use of back-end digitization step realized by mostly digital circuitries differentiate it from other counterparts which are commonly implemented using either amplifiers or amplifier-based comparators. The proposed design is implemented using TSMC 0.18mum CMOS standard process with 1.5V supply voltage. It consumes only a few hundred nanowatts (486nW) at a sampling frequency of 500 kS/s for an input current of 8 muA, which equals half of the full-scale range of our ADC. Furthermore, the new ADC structure presents a maximum differential non-linearity (DNL) and a maximum integral non-linearity (INL) of less than 0.16 LSB and 0.41 LSB, respectively.;The proposed architecture inspired by physiological neuron mainly consists of the following three modules: (1) Generator of constant amplitude pulses, where their number is proportional to an input sufficient current (greater than 100 nA). This module is called neuron cell due to its similarities to a neuron. It transmits information by generating the actions potentials (APs). The implementation of this module is based on the mathematical model of Hodgkin-Huxley which describes the electrical behavior of a physiologic neuron; (2) Systolic asynchronous counter of APs, which provides 8-bit quantized value corresponding to the input current; (3) Calibration circuit operating as a charge-pump to improve the integral non-linearity of the NC-ADC.;The choice of adequate architecture considerably relies on the nature of the application. Successive approximation (SA) ADCs are reported to be good candidates for our application considering their minimal requirement to active analog circuitries. However, for the sampling rates lower than 100 kS/s, they are remarkably constrained by the comparator offset, the DAC linearity and the overall power consumption. Therefore, these effects have significant impact on their performance.
Keywords/Search Tags:ADC, Power consumption, Adcs, LSB
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