Research And Design Of The ASK Modulation RFID Reader On 125KHz

With the rapid development of the Internet of things,RFID technology,as the core technology of the Internet of things,has also developed rapidly.As a non-contact automatic identification communication technology,it has the characteristics of long life and large storage information compared with the traditional barcode identification.For RFID system,a reader controls many tags,but there are many kinds of tags,the most important is the difference between signal modulation mode and signal transmission rate,so a reader that can read multiple transmission rates can be better applied to different application systems.And some reader chips do not integrate the demodulation circuit,only filter and decode functions.When users design a reader,they need to design demodulation circuit outside the reader chip,so the application circuit scale of the chip will be larger.The main work of this paper is to research and design the 125 k Hz reader chip.The reader chip mainly aims at the tag chip which uses amplitude modulation to send data,and designs the analog circuit and digital control circuit of the chip.A new demodulation method is used to demodulate the amplitude modulated signal.Used a sample and hold circuit to instead the envelope detector diode in the amplitude modulated signal demodulation,sampling the peak envelope of the input signal,which reduces the diode turn-on voltage loss and the requirement for the input voltage amplitude.In order to keep the sample and hold circuit sampling at the peak point of the input signal,a phase measurement unit is used to detect the phase of the input signal and compare it with the local clock to ensure that the sample and hold circuit is kept at the peak point of the carrier to reduce the envelope loss.Compared with the traditional envelope detection,it has higher sensitivity.In order to demodulate different transmission rates and for different input signal amplitudes,an active switched capacitor filter and amplifier are used to filter and amplify the signal after sample and hold.The filter frequency and the magnification of the amplifier are selected by the user according to the transmission rate of the tag through the command of MCU.The filter frequency for 2kbit/s and 4kbit/s transmission rate is 3k Hz and 6k Hz.The magnification of the amplifier can choose 100,200,500 and 1000 times.This paper designs and simulates based on CSMC0.5?m process,designing the digital circuit using logic gate and D-flip-flop.The final simulation results show that in a power supply voltage is 5V and the 125 k Hz carrier frequency,the minimum input voltage that can be correctly demodulated for a 2kbit/s or 4kbit/s bi-phase code signal is 7.5m V.The minimum bit voltage difference is 0.7m V,which increases the sensitivity of the demodulator.According to the external input instructions,the digital circuit also completes the control function of the analog circuit.