A Design Of SPDT Analog Switch Chip Based On SOI All-Dielectric Isolation Process

As a branch of analog switches,CMOS analog switches now have more and more application scenarios,including various industrial equipment,control terminals,etc.,and CMOS analog switches based on SOI process greatly improve the CMOS analog switch The performance makes it more suitable for some more demanding scenarios,such as aerospace,high-precision data sampling,and so on.This article aims to design a CMOS analog switch chip with SOI all-dielectric isolation process,which contains dual-channel single-pole double-throw analog switches.Its operating temperature range is-55 ? ~ + 125 ?,and two power supplies of ± 15 V are required.The SOI all-dielectric isolation process adopted by it brings many advantages such as lower on-resistance,faster switching speed,no latch-up effect,high integration,low parasitic effect and high radiation resistance.It is also compatible with standard CMOS and TTL levels.In this design,we first developed the required SOI CMOS process in cooperation with process manufacturer CSMC.Using TSUPREM4 process simulation software to complete the design and simulation of the process flow;using the device simulation software MEDICI to design and simulate the required devices,for the power MOS devices used in the design,we simulated its threshold voltage,breakdown voltage and conduction Parameters such as on-resistance.Then based on this process and device,the internal circuit of the chip was designed and simulated.The simulation used the circuit simulation software Cadence.During the simulation,the basic functions of the analog switch and the design requirements parameters such as on-resistance,leakage current and conversion time were mainly targeted.Tested and optimized the circuit structure according to the simulation results,such as floating the connection of the substrate of the key power switch tube to reduce its on-resistance,etc.,and the results of the simulation finally met the original design requirements;Afterwards,Cadence software was used to draw the layout based on the previously designed circuit.Finally,10 finished chips that had been taped were taken for overall performance parameter testing.After simulation,the maximum on-resistance at normal temperature is 70?,the leakage current is 0.4nA,the switching delay is 73 ns,and the power supply current is 169?A.After testing,the final on-resistance is 34.2?,the leakage current is 0.492 nA,the switching delay is 186.0ns,and the power supply current is 130.121?A.After testing,all parameters of the chip meet the initial design requirements.