Optimization Of High And Low Threshold Independent Gate TFET Devices

FinFET has become the mainstream device of current integrated circuits.The threedimensional Fin structure allows the gate to cover the channel in a large area,which effectively increases its' gate control ability.This structure can improve the subthreshold swing of the device,reduce the leakage current and improve the on current.The performance of 3D structure FinFET is far beyond the planar CMOS.But as the development of integrated circuits,which following Moore's Law,the device sizes lasted to decrease.The most advanced device size has reached 7nm so far,and the challenges of FinFET device manufacturing process and circuit design have risen.For example,traditional CMOS devices with a subthreshold swing limit of 60mV/dec gradually become unsuitable for low-power circuit design under lower supply voltage.The requirement of new devices to meet these circuit design is aroused consequently.Tunneling field effect transistor(TFET),with the current transmission mechanism of inter-band tunneling,can reduce the subthreshold slope to below 60mV/dec and has a large switching current ratio,which is suitable for low power integrated circuit design.The advantages of this device are significant,yet still remain some problems.Therefore,this paper aims at designing a self-contained gate TFET device,which can improve the on-current of the device,and can be flexibly used in circuit design and increase circuit integration densityIn this thesis,an independent gate high and low threshold TFET device is proposed and verified by TCAD.The article first compares TFET and FinFET and then improves TFET performance in structure and material respectively.Finally,the individual gate devices are specifically optimized for better electrical performance.This article includes the following five parts of research content:1.Explain the problems and challenges faced by TFET devices at present,and comparing TFET with current mainstream devices.The advantages and disadvantages of TFET as a new device are analyzed.2.Summarizing the main problems in TFET device design.Review domestic and foreign literature,summarize the optimization design method to solve the main problems of the device.3.Optimization of the structure of TFET is carried out.Using TCAD device to simulate and analyze device performance for the single-gate structure,double-gate structure,gate overlay structure and other structural optimization methods.4.Structural optimization of the TFET is performed.Due to the limited improvement of device in structural design,it is proposed that with the optimization of the material can improve the electrical performance more effectively.Simulation analysis of homojunction/ heterojunction devices of silicon germanium and III-V materials was performed with TCAD.5.Optimization of the independent gate high and low threshold TFET devices is performed.Since the independent dual gate device needs to accomplish the 'and' 'or' switching logic under different gate input,the device is further-optimized in this paper.The performance of the designed independent gate high and low threshold devices is analyzed in simulations and the switching logic was verified.TCAD simulation results show that the independent gate high and low threshold devices device meet the expectations of switch logic design.Its low-threshold device can accomplish 'or' logic,which is equivalent to two discrete devices connected in parallel.Also high-threshold device can accomplish 'and' logic and it's equivalent to two discrete devices connected in series.Further more,simulation results also show that this device has higher on-state current and lower subthreshold slope compared to silicon-based TFET,meeting the requirements of low power IC design as well.