Specialized Design Of RISC-V ISA For Network Packet Forwarding

A rapidly rising in netwrok transport rate calls for a higher processing performance of network packet forwarding.However,the performance gap between the slow I/O devices,the memory and high-speed processing unit greatly affects packet processing performance.And the limited on-broad storage space exacerbrates this gap.At the same time,various types of network services and protocols involved in the network packet forwarding call for considerable programmability.Although the classic hardware accelerators have performance advantages,they are lack of flexibility and can not adapt to the rising demand for network services.In order to make full use of on-chip storage space resources,reduce the overhead of access failure and improve the performance of device processing,this paper focuses on improving network packet forwarding performance throuhg specializing RISC-V ISA.We design compressed instruction set and specific instructions.This can improve performance from two aspects.For one thing,compressed instructions reduce the executable code size so that there is a decrease in I/O overhead and the times of accessing memory caused by instruction misses.For another,specialized instructions contribute to kernel computing,which help to increase the code density and improve processing performance.In our experiment,with using compressed instructions,the static codes compression ratio goes down to 70% and dynamic codes compression rate is 90%,the instruction miss rate is reduced by 30%-70%.On the other hand,under the same conditions,processing performance doubles and dynamic codes compression rate achieves 35% to 65% with the use of specialized instructions.