Research On Marching-on In-time Scheme And The Fast Algorithm Of Time Domain Integral Equation

In order to better study the advantages and performance of LDPC code in ultra-HD video wireless transmission,and to adapt to the code length bit rate required by various codes,this paper studies the compatible structure of eight LDPC multi-mode from the aspects of multi-code length and multi-code rate,and optimizes the coding and decoding algorithm to make it easy to be implemented by FPGA.Firstly,this paper gives the check matrix structure of pseudo random LDPC code and analyzes the significance of its corresponding parameters in the realization.Secondly,the coding algorithm and sum product decoding algorithm of LDPC are introduced,and the difficulties in FPGA implementation are analyzed in detail.QPSK modulation demodulation and then,from the concrete way and the additional additive white gaussian noise simulation scenario,the use of dynamically generated ng Luo Huayu address way to improve the structure of the implementation of coding algorithm,and by using linear fitting way to optimize the structure of the realization of decoding algorithm,the encoding decoding algorithm can save a lot of FPGA resources in the implementation of cases,the performance loss is minimal.Then,using VERILOG language in VIVADO software,the optimized coding and decoding algorithm is used to realize 8 LDPC coding and decoding modules compatible with different modes.Finally,on the FPGA platform structures,conforms to the situation of LDPC multimodal test platform of decoding module,after implementation of eight kinds of mode compatible LDPC encoding decoding module to carry on the test platform performance testing,test platform can collect QPSK modulation demodulation in additional additive white gaussian noise(number of LDPC error for performance analysis.The test results show that the optimized encoding and decoding algorithm can save about 98% of THE FPGA likelihood ratio to compute storage resources,can carry out burst mode changes,and the mode with the largest throughput can reach a maximum of 25 M.For the first four modes with a bit rate of 1/2,the performance of the implemented module is only 0.1~0.2dB lower than the SNR performance required.For the last four modes with a bit rate of 3/4,the performance of the realized module is only 0.1~0.3dB lower than the SNR performance required.The LDPC coding and decoding module compatible with eight modes based on the optimized algorithm can achieve the required performance well and save a lot of FPGA resources required for implementation,making it easy to implement.